//Stephen Kirksharian
//Robert Harkreader
//CPSC 321
//DUE 4/27/08

module registerFile(readregister1,readregister2,writeregister,writedata,readdata1,readdata2,write_enable,Reset_b,clock);
	
	input [31:0]writedata;
	input [4:0]readregister1,readregister2,writeregister;
	input write_enable,clock,Reset_b;
	
	output [31:0]readdata1,readdata2;
	
	reg [31:0]readdata1,readdata2;
	//In the reg file, these will be our registers
	reg [31:0] reg_files [31:0]; 
	//This is used to tempREGorary initialize the registers to zero
	reg [4:0]tempREG; 
	//assuming that registers declared here will start at 0

	//Initializing...  output will be x until initialized	

	always @(~Reset_b) begin
	  tempREG=0;
	  repeat (31) begin
		reg_files[tempREG]=0;
		tempREG=tempREG+1;
	  end
	  assign readdata1=0;readdata2=0;
	end
		
	//If there is any change, then the important variables should cause us to change everything
	always @(posedge clock)
	  begin
		readdata1=reg_files[readregister1]; readdata2=reg_files[readregister2];
	  end

	//We need to write on this clock edge and read this at the postive edge
	always @(negedge clock)
	  begin
		if(write_enable==1) begin
			if(writeregister!=0) 
			   reg_files[writeregister]=writedata;
		end
	  end

endmodule
